Antmicro @antmicro
Antmicro is a software-driven tech company developing open and modern industrial edge and cloud AI systems. antmicro.com Joined May 2011-
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Visit @FossiFoundation's ORConf to learn about the ongoing work on implementing TMR into the @risc_v VeeR-EL2 core and new open source tools developed around Verilator for fault injection testing: fossi-foundation.org/orconf/2026#op… @CHIPSAlliance
Listen to our @FossiFoundation ORConf talk to discover how open source tools and cores hosted by @CHIPSAlliance, such as @risc_v VeeR, and the @OpenROAD_EDA Initiative help accelerate the ASIC development process: fossi-foundation.org/orconf/2026#im… @GoogleOSS
Join us at @FossiFoundation's ORConf to learn about the latest developments in SystemVerilog support in Verilator: four-state logic, constrained randomization, SVA, UVM, and related tooling such as our Coverview coverage dashboard: fossi-foundation.org/orconf/2026#cl… @CHIPSAlliance
Read how @ADI_News is leveraging @renodeio to develop, test and validate software on virtual @Arm-based platforms before physical hardware is available, and see how Renode complements ADI's development workflow: antmicro.com/blog/2026/09/h…
Achieve faster and more efficient ASIC power profile estimation using our peak, glitch, and scoped power analysis workflows built around the @OpenROAD_EDA toolchain. See how to use them to identify power irregularities in your digital designs: antmicro.com/blog/2026/08/p… @GoogleOSS @UCSD @Siemens
ORConf by @FossiFoundation is coming soon to Ghent! Once again, Antmicro is sponsoring one of the most interesting conferences on open source silicon design. Join us for talks on four-state logic support in Verilator, fault injection in the @risc_v VeeR core, and latest news from the @CHIPSAlliance SV Tools Project fossi-foundation.org/orconf/2026
Join Antmicro at @NVIDIAGTC 2026 in Berlin to discover a range of open hardware baseboards for Jetson Thor and Jetson Orin and our open source toolkit for the Jetson ecosystem: custom Yocto-based BSPs, factory testing with Protoplaster, AI optimization and deployment with Kenning and smart OTA update systems with RDFM nvidia.com/en-eu/gtc/ @NVIDIARobotics
Check out Faultergeist: a framework for generating and injecting bit-flips into hardware designs using Verilator. To start with, Faultergeist is equipped with generation models simulating faults caused by cosmic radiation, aiding in testing space and critical applications: antmicro.com/blog/2026/08/S…
The new @nvidia Jetson Orin Nano 2 SoM offers enhanced entry-level edge AI performance & power efficiency. See how our designs, tools & services can help you take full advantage of the new module, from prototype to final product: antmicro.com/blog/2026/08/e… @nvidia_AI @nvidiaRobotics
Simulate the @Toyota open source RAMN platform in @renodeio to test automotive CAN and CAN-FD networks without the need for physical hardware. The virtual setup can be connected to @carlasimulator for more accessible, versatile development and testing: antmicro.com/blog/2026/08/t…
We're approaching 1K supported platforms in our @renodeio @ZephyrIoT dashboard! Read about the recent improvements to the Zephyr & U-Boot dashboards: improved @risc_v support and an updated UI w/ a Run in Renode option, dark mode & more: antmicro.com/blog/2026/08/r… @linuxfoundation
CHIPS Alliance’s open source I3C Core now includes Host Controller support implemented by @antmicro. The Controller can assign Dynamic Addresses, send commands, read/write data, and manage bus ownership. chipsalliance.org/news/implement…
Antmicro offers its open source toolkit and service portfolio around the Jetson ecosystem to help customers build and deploy scalable and more cost-efficient robotic/edge AI systems powered by the new Jetson Thor T2000 & T3000: antmicro.com/blog/2026/08/a… @NVIDIARobotics @NVIDIAAI
Our open hardware Thunderbolt to 10GbE Adapter, developed by combining two of our previous designs, can help you bring high-speed network connectivity to Thunderbolt-enabled devices. Read more about the adapter and customization options: antmicro.com/blog/2026/07/o…
We've introduced a range of UI and functional improvements to our open source Pipeline Manager, which allow you to represent complex systems and data flows in even more versatile and streamlined ways: antmicro.com/blog/2026/07/p…
We are excited to announce that Antmicro joined the @OpenROAD_EDA Initiative to enable a collaborative and fully transparent digital design ecosystem built around open source tools. Read how we help bring open innovation to chip design: antmicro.com/blog/2026/07/a… @Google @UCSanDiego
At the @DACconference Open Source EDA BoF, Antmicro will join a panel discussing the skill set needed for future silicon designers to shift from the traditional "how" to the crucial "what" in the age of AI-assisted workflows …urce-eda-birds-of-a-feather.github.io @CHIPSAlliance @linuxfoundation
CHIPS Alliance will join the Open Source EDA BoF at @DACconference 2026 on July 28. Michael Gielda (@antmicro) will share CHIPS Alliance updates, and Krzysztof Bieganski (@antmicro) will cover four-state logic & UVM compatibility in Verilator. 🔗chipsalliance.org/news/chips-all…
An initial milestone has been reached in @antmicro’s work on four-state logic in Verilator. The proposed implementation uses the experimental --fourstate flag. Significant Verilator efforts converge in the CHIPS Alliance SV Tools Project. 🔗 chipsalliance.org/news/initial-i…
Our 2nd talk at the Open Source EDA BoF @DACconference session will discuss efforts towards an important milestone for Verilator: 4-state logic, improvements in UVM compatibility, and other developments in @CHIPSAlliance SV Tools Project: …urce-eda-birds-of-a-feather.github.io @linuxfoundation
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